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l q qt300 c apacitance to d igital c onverter capacitance to digital converter (cdc) ic direct-to-digital conversion, 16 bits log response: wide dynamic range outputs raw data to a host device single wire uart interface master or slave mode spi interface programmable clock speed turns objects into intrinsic touch sensors one external sample capacitor to control gain multiple qt300?s possible on one spi bus the qt300 charge-transfer (?qt??) ic is a self-contained capacitance-to- digital-converter (cdc) capable of detecting femotofarad level changes in capacitance. while designed primarily for instrumentation applications, it can be used also for touch control applications where signal processing is best handled by a host mcu. primary applications include fluid level sensors, distance sensors, transducer ?amplifiers? for pressure and humidity sensing functions, material detectors, and other uses requiring quantified capacitance data. unlike other quantum products, the qt300 does not process its acquired data. its only result is raw, unprocessed binary data which can be transmitted to a host via either a bidirectional spi interface or a simple polled single wire uart type interface. this allows the designer to treat the device as a capacitance-to-digital-converter (cdc) for measurement applications. it is ideal for situations where there are unique signal processing requirements. the device requires only a single sampling capacitor to function. the value of this capacitor controls the gain of the sensor, and it can be adjusted over 2? decades of range from 1nf to 500nf. no external switches, opamps, or other components are required. the device operates on demand, and can be synchronized to allow several qt300?s to operate near each other without cross-interference. l q copyright ? 2002 qrg ltd qt300 r1.01 21/09/03 sdo vdd req / 1w sns2 vss sns1 sck drdy 1 2 3 45 6 7 8 qt300 - qt300-is -40 0 c to +85 0 c QT300-D - 0 0 c to +70 0 c 8-pin dip soic t a available options applications fluid level sensors prox sensors moisture detection position sensing transducer driver material sensors
positive supply vdd 8 serial data out sdo 7 request input /req 6 sense 2 line sns2 5 negative supply (ground) vss 4 sense 1 line sns1 3 serial data clock sck 2 data ready /drdy 1 function name pin table 1-1 spi mode pin description positive supply vdd 8 connect to vdd or vss - 7 1w uart line 1w 6 sense 2 line sns2 5 negative supply (ground) vss 4 sense 1 line sns1 3 connect to vdd or vss - 2 connect to vdd or vss - 1 function name pin table 1-2 1w uart mode pin description serial clone data out sdo 7 serial clone data in sdi 6 serial clone data clock sck 2 function name pin table 1-3 alternate cloning pin functions 1 - overview the qt300 is a digital burst mode charge-transfer (qt) capacitance-to-digital converter (cdc) designed for applications requiring raw signal information such as fluid level sensing and distance gauging; it outputs raw digital signal data over a serial interface. the output data is in a 16-bit format; signal levels depend on load (cx) and the sampling capacitor value (cs). 1.1 basic operation the qt300 does no internal signal processing; data is simply returned via one of two serial port types. there are two basic types of serial interface: 4-wire spi and a simple single wire ( ? 1w ? ) uart. the spi interface allows multiple devices to be connected on one spi bus, while the1w uart requires that the controller have one dedicated pin for each qt300. there are two types of spi mode, master and slave. the type of serial port and its mode can be selected via the cloning process using a qtm300ca programming adapter. the qt300 operates only on request from a host device. after initiation via a trigger signal, the qt300 generates an acquisition burst and sends the resulting raw signal data back via one of the serial modes. 1.2 cs / cx dependency the value returned is a direct function of cs, the fixed sample capacitor and cx, the unknown or variable capacitance. these two values influence device sensitivity and response time, making them very important parameters. sensitivity is also a function of electrode size, shape, orientation, the composition and aspect of the object being sensed, the thickness and composition of any dielectric overlaying the electrode, and the degree of mutual coupling between the electrode and the object being sensed. the response follows a logarithmic curve (figures 7-4, 7-5, page 10); each doubling of cs increases the signal level and differential sensitivity by a factor of 2. likewise, doubling cx reduces the signal level and differential sensitivity by a factor of 2. 2 - timing figure 2-1 shows the basic qt300 acquisition timing parameters. the basic timing parameters are: tbd burst duration (2.1) tacq acquire response time (2.2) tbs burst spacing (2.3) 2.1 tbd - burst duration the burst duration depends on the values of cs and cx and to a lesser extent, vdd. the burst is composed of charge-transfer cycles operating at about 240khz. l q 2 qt300 r1.01 21/09/03 figure 1-1 basic qt300 circuit in spi mode. 4 3 8 5 sdi sck drdy sdo 2 sck drdy req req gnd 6 7 1 vcc qt 300 vdd cs 100nf sns 1 sensor host micro sns 2 figure 1-2 basic qt300 circuit in uart mode. 4 8 rx (1w uart) 2 host micro 6 1 7 vss 3 5 sns1 sns2 electrode vdd 1w qt300
the length of this burst is an important parameter as it is directly related to the signal value. the burst duration also affects the response time of the sensor; the larger cs is, the longer the burst, the slower the possible acquisition rate. 2.2 tacq - acquire response time the time from the /req or 1w line going low until the completion of data transmission is tacq. tacq depends on the acquisition burst length as well as the serial transmission time. spi mode: in spi mode tacq depends in part on the serial clock speed and the space between the returned high and low bytes. in spi slave mode the clock speed and the inter-byte spacing time tbdly is determine by the host. in spi master mode these timings are set by setup parameters scd and mls. 1w mode: tacq depends in part on the baud rate as well as the inter-byte spacing. the baud rate is auto-set by the trigger pulse width; the inter-byte spacing is set by the mls parameter. see section 4. 2.3 tbs - burst spacing burst spacing is the time from the start of one acquisition burst to the start of the next burst. it depends on the host ? s trigger rate on the /req or 1w pin. the qt300 only acquires when the host requests it. while waiting for a new request the part is in a low power mode. 3 - spi port 3.1 spi specifications the qt300 can operate in master or slave mode, and thus is compatible with virtually all spi-capable microcontrollers. the spi interface has the following specifications: max clock rate, fckm 40khz (master mode) max clock rate, fcks 40khz (slave mode) data length 2 bytes (16 bits total) inter-byte delay 8 s (master mode)* 12 s (slave mode) clock idle logic level low or high* clock edge data out on rising or falling edge* data sequence high byte first, msb first *determined by setups the host can clock the spi at any rate up to and including the maximum. the maximum clock rate of the part in master mode is determined in setups via cloning. 3.2 protocol overview the qt300 only transmits data on request, after an acquisition burst. the host requests an acquire by setting the /req line low for at least 30 s; the device then acquires. when finished, the drdy line is pulled low by the qt300 to indicate it is ready to send data. (figure 2-1). the transfer is done as two bytes, with the highest byte transferred first. in master mode, /drdy goes high between bytes for the period determined by setup parameter mls; this is a multiple of 6 s. when not communicating, all spi lines float to allow multiple chips to connect over the same spi lines. a pullup or pulldown resistor is required on sck depending on the selected clock phase, determined by setups. a pullup resistor is required on /drdy. /req may require a pullup if the host ever allows this line to float. 3.3 spi bus sharing all spi float transfers making it possible to have several qt300 devices (or other unrelated devices) share the spi control signals (figure 3-1). each part needs an individual /req line, but /drdy, sck and sdo can be connected together. 3.4 spi slave mode refer to figure 7-1 and table 7-1, page 8. in spi slave mode, /drdy is used to let the host know when data is ready for collection in response to a request so that the host can clock over the data. spi slave mode uses 4 signals: /req - request acquisition input; active low input-only. when /req is pulled low, the qt300 wakes and starts an acquire. the ic will transmit the resulting data only when the acquire has finished. /req should return high before the end of the burst . if /req is still low at the end of the burst the part will go into setup mode. the minimum duration of /req is 30 s. l q 3 qt300 r1.01 21/09/03 figure 2-1 signal acquisition - slave spi mode
sdo - serial data output; output-only. this is the data output to the host during an spi transfer. when not in use, this pin floats. this pin should be connected to the sdi input pin of the host device. sck - spi clock; idle high or idle low; input-only spi clock from the host. the idle state is determined in setups by the serial mode (sm) parameter. if sm is set for idle-low sck: data is shifted out of the qt300 on the rising edge of sck and should be shifted into the host on the falling edge of sck. if sm is set for idle-high sck: data is shifted out of the qt300 on the falling edge of sck and should be shifted into the host on the rising edge of sck. the maximum clock speed is 40khz, and the timings should obey the parameters tskh and tskl in table 7-1. /drdy - data ready; active low output only. this indicates to the host that the device is ready to send data back to the host. during idle times this pin floats and therefore must be connected to a pullup resistor. the host must wait until /drdy goes low before starting an spi transfer. between the high and low byte clockings, the host should observe a delay of 12 s. a typical spi slave mode communication sequence is: 1) host pulses /req low for 30 s to initiate an acquire. 2) qt300 acquires a signal in response to /req. 3) qt300 pulls /drdy low when ready to send data back. 4) host detects /drdy is low. 5) host clocks out the high byte of data from the qt300. 6) host waits for 12 s. 7) host clocks out the low byte of data from the qt300. 8) qt300 releases /drdy to float high. 3.5 spi master mode refer to figure 7-2 and table 7-2, page 8. in master spi mode the qt300 generates the clock signal after an acquire initiated from the host via the /req line. the clock speed and the spacing between the two bytes is set via the setup process (section 6). scd setup parameter determines the master-mode clock rate. the default value is 55 (resulting in a 2.55khz rate). the relationship is: fscd = 1200/(30+ (scd x 8)) in khz where scd = 0..255 mls setup parameter determines the spacing between the two return bytes; this can be important to allow a slow host device to recover from receiving the first byte to prevent an overrun. the default value is 148 (resulting in a 500 s gap). the relationship is: tmls (in s) = (10 + mls x 4) / 1.2 where mls = 0..255 (from user setup mls) master spi mode requires at least 3 signals to operate: /req - request acquisition input; active low input-only. when /req is pulled low, the qt300 wakes and starts an acquire. the ic will transmit the resulting data only when the acquire has finished. /req must return high before the end of the burst. if /req is still low at the end of the burst the part goes into setup mode. the minimum duration of /req is 30 s. sdo - serial data output; idle low output-only. this is the data output to the host during an spi transfer. when not in use, this pin floats. this pin should be connected to the sdi input pin of the host device. sck - spi clock; idle high or idle low, output-only. the idle state is determined in setups by the serial mode (sm) parameter. if sm is set for idle-low sck: data is shifted out of the qt300 on the rising edge of sck and should be shifted into the host on the falling edge of sck. if sm is set for idle-high sck: data is shifted out of the qt300 on the falling edge of sck and should be shifted into the host on the rising edge of sck. the maximum clock speed is 40khz , and the timings should obey the parameters tskh and tskl in table 7-2. /drdy - data ready (optional); active low output only. this indicates to the host that the device is ready to send data l q 4 qt300 r1.01 21/09/03 figure 3-1 multiple qt300's on the same spi port req1 req2 8 4 8 4 8 4 host micro sck 6 6 6 5 sns 1 5 sns 1 5 sns 1 sensor sensor sensor req3 sdi 7 1 qt 300 7 2 1 qt 300 7 2 1 qt 300 cs sns 2 vcc vdd 100nf cs sns 2 3 vcc 100nf 3 cs sns 2 100nf vdd 2 vdd 3 vcc drdy sck sck sck gnd req sdo drdy sdo req gnd drdy gnd sdo drdy req
back to the host. during idle times this pin floats and therefore must be connected to a pullup resistor. the drdy line can be used as a slave select line (ss). the host does not need this line to operate in many cases. drdy can be used to 'frame' byte transmissions. between bytes /drdy will go high for a period determined by the mls setup parameter; the minimum period is 8.3 s. a typical master mode spi sequence is: 1) host pulses /req low for 30 s. 2) qt300 acquires a signal in response to /req. 3) qt300 pulls /drdy low when ready to send data. 4) host detects /drdy low and prepares to receive data. 5) qt300 clocks out first byte of data (msb). 6) qt300 sets /drdy high for a duration determined by setup parameter mls. 7) qt300 pulls /drdy low. 8) qt300 clocks out the low byte (lsb). 9) qt300 releases /drdy to float high. 4 single-wire (1w) uart interface the single wire ('1w') uart option allows all communications to take place over a single bidirectional line with a 10k pullup resistor. the host device triggers the qt300 to acquire by means of a pulse sent to the qt300 over the wire. the baud rate is established by the width of this pulse; the pulse width establishes the bit rate of the uart transmission to follow. the qt300 then acquires, and responds by sending two bytes of data back over the 1w line with a delay between the bytes as determined by parameter mls. 1w operation permits a device to be controlled from a single pin on a host controller, using either a hardware or software uart. several qt300 ? s can coexist on a single host pin, provided there is some logic steering. this mode is set via the cloning process using parameter sm (see section 6). 4.1 1w uart specifications the qt300 operates in 1w uart mode with the following specifications: baud rate range 4,800 to 9,600 bits/sec data length 2 bytes (16 bits total) stop bit 1 (each byte) parity none idle state high the 1w line must have a pullup resistor on it (i.e. 10k), or 1w communications will not function. 4.2 uart 1w protocol the qt300 acquires and transmits only on request. the sequence is: 1) the host generates a pulse on the 1w pin; the pulse width must match the baud rate (bit width) of the expected return baud rate from the qt300. this pulse actually sets the baud rate each time, and so it can vary from one acquire to another. see section 4.3 and figure 4-1. 2) the 1w pulse width is measured by the qt300 to determine the baud rate. 3) the host floats 1w high. 4) the qt300 acquires the signal to completion. 5) qt300 returns data in the following uart format: start bit (low) 8 bits, high byte stop bit (high) delay (determined by mls setup) start bit (low) 8 bits, low byte stop bit (high) 6) the qt300 floats the 1w line and enters idle mode. l q 5 qt300 r1.01 21/09/03 figure 4-1 uart and trigger pulse signal.
4.3 trigger pulse description the part wakes from low power mode when the first negative edge is detected on the 1w pin (figure 4-1, bottom). the negative pulse must be at least 30 s wide. the host then generates the positive pulse that actually sets the baud rate. the qt300 measure this pulse and uses its length to set the baud bit (shift out) rate. 30 s (or more) of logic-low must follow this pulse. the host must then float the 1w line to allow the qt300 to start the signal acquisition. 5 circuit guidelines 5.1 sample capacitors cs capacitors can be virtually any plastic film or low to medium-k ceramic capacitor. the normal usable cs range is from 1nf ~ 500nf depending on the sensitivity required; larger values of cs require higher stability to ensure low drift. acceptable capacitor types include np0 or c0g ceramic, pps film, and y5e and x7r ceramics in that order. 5.2 power supply 5.2.1 s tability the qt300 makes use of the power supply as a reference voltage. the acquired signal will shift slightly with changes in vdd; vdd fluctuations often happen when additional loads are switched on or off such as leds etc. if the power supply is shared with another electronic system, care should be taken to assure that the supply is free of spikes, sags, and surges. it is best practice to use a regulator just for the qt300 (or one for a set of qt300's). 5.2.2 s upply r equirements vdd can range from 2 to 5 volts nominal. current drain will vary depending on vdd. during writing of the internal eeprom, vdd must be at least 2.2 volts. if desired, the supply can be regulated using a conventional regulator, for example cmos ldo regulators, or standard 78lxx-series 3-terminal devices. for proper operation a 100nf (0.1uf) ceramic bypass capacitor must be used between vdd and vss; the bypass cap should be placed very close to the vdd and vss pins. 5.3 pcb layout 5.3.1 g round p lanes the use of ground planes around the device is encouraged for noise reasons, but ground or power should not be coupled too close to the sense pins in order to reduce cx load. likewise, the traces leading from the sense pins to the electrode should not be placed directly over a ground plane; rather, the ground plane should be relieved by at least 3 times the width of the sense traces directly under it, with periodic thin bridges over the gap to provide ground continuity. 5.3.2 n oise s ynchronization external fields can cause interference leading to a noisy and unstable signal. the most common external fields usually are from ac mains power. the /req line of the qt300 can be used to synchronize the acquisition to a repetitive external source of interference such as the power line frequency in order to dramatically reduce signal noise. if line frequency is present near the sensors, this feature should be used. 6 parameter setups cloning a special interface is provided to allow user-defined setups to be loaded into internal eeprom or read back out for development and production purposes. the qtm300ca cloning board in conjunction with qt3view software simplifies the setups cloning process greatly. the e3a eval board has been designed with a connector to facilitate direct connection with the qtm300ca. the qtm300ca in turn connects to any pc with a serial port which can run qt3view software (included with the qtm300ca and available free on quantum ? s web site). the connections required for cloning are shown in figure 6-1. further information on the cloning process can be found in the qtm300ca instruction guide. the parameters which can be altered are shown in table 7-4. the internal eeprom has a life expectancy of 100,000 erase/write cycles and the minimum voltage for a write cycle is 2.2 volts. a serial interface specification for the device can be obtained by contacting quantum. l q 6 qt300 r1.01 21/09/03 figure 6-1 clone interface wiring 5 sck gnd 4 8 3 6 sck vcc sdi sdo sdo gnd 7 2 drdy req 1 vdd qt 300 cs 100nf sns 1 sck sensor sdi sns 2 drdy req cloning signal
7 electrical specifications 7.1 absolute maximum specifications operating temp ................................................................................ as designated by suffix storage temp ....................................................................................... -65 o c to +125 o c v dd ...................................................................................................... -0.5 to +6v max continuous pin current, any control or drive pin .............................................................. 40ma short circuit duration to ground, any pin ......................................................................... infinite short circuit duration to v dd , any pin ............................................................................ infinite voltage forced onto any pin .................................................................... -1v to ( vdd + 0.5) volts 7.2 recommended operating conditions v dd ........................................................................................................ +2 to 5v v dd min required to reprogram eeprom setups ................................................................... +2.2v short-term supply ripple+noise .................................................................................. 5mv long-term supply stability .................................................................................... 100mv cs value................................................................................................. 1 to 500nf cx value..................................................................................................0 to 100pf 7.3 ac specifications vdd = 3.0, ta = recommended operating range, cs=100nf unless noted s 30 request pulse t rqp cs = 4.7nf to 200nf; cx = 0 ms 25 0.5 burst length t bl ns 830 char g e/transfer duration t pc notes units max typ min description parameter 7.4 dc specifications vdd = 3.0v, cs = 10nf, cx = 5pf, ta = recommended range, unless otherwise noted figs 7-4, 7-5 ff 7 1,000 resolution per bit s bits 16 acquisition resolution a r v vdd-0.6 high output voltage v oh v 0.4 low output voltage v ol v dd = 2.5 to 5.0 v v 0.6 vdd in p ut hi g h volta g e v ih vdd = 2.5 to 5.0v v 0.3 vdd input low voltage v il dependent on duty cycle a 1,500 60 supply current i dd v 5.5 2 supply voltage v dd notes units max typ min description parameter l q 7 qt300 r1.01 21/09/03
l q 8 qt300 r1.01 21/09/03 figure 7-1 spi slave mode sck {from host} sdo {from qt300} d15 drdy {from qt300} d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 tskd tsk h ts kl thso ts o s h tmls tds figure 7-2 spi master mode sck {from qt300} sdo {from qt300} d15 drdy {from qt300} d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 tds ts o s h thso t mls tskd tsk h ts kl s 1,000 12 drdy low to sck high delay t ds s 1,000 12 msb-lsb spacing t mls s - 7 sdo hold time t hso s 10 - sck high to sdo ready setup time t sosh s - 12 sck low duration t skl s - 13 sck high duration t skh s - 25 clock duration t skd units max min parameter symbol table 7-1 slave spi timing - - 12.5 drdy low to sck high delay t ds s 1,708 8.3 msb-lsb spacing t mls - - 12.5 sdo hold time t hso s 7 4 sck high to sdo ready setup time t sosh s 862.5 12.5 sck low duration t skl s 862.5 12.5 sck high duration t skh s 1,725 25 clock duration t skd units max min parameter symbol table 7-2 master spi timing
l q 9 qt300 r1.01 21/09/03 figure 7-3 1w uart mode 1w uart twu tbr ts b tacq ts t ar t tstop tmls 8bits msb 8bits lsb s 8 x tbr - lsb s 8 bits data, lsb first 8 x tbr - msb s - 850 8 msb-lsb spacing tmls - tbr stop pulse tstop - tbr start pulse tstart ms depends on cs and cx 400 - acquisition time tacq % - 2 baud rate match accuracy - 9,600 4,800 baud rate range s - 5,000 30 baud end level tsb s - 210 104 baud set pulse tbr s - 5,000 30 wake level twu units notes max min parameter symbol table 7-3 1w uart timing table 7-4 setups summary chart s tmls = (10 + (mls x 4))/1.2 148 0 - 255 mls msb-lsb spacing s tscd = (30 + (scd x 8))/1.2 55 0 - 255 scd clock speed slave clock idle high 4 slave clock idle low 3 master clock idle high 2 master clock idle low 1 - - 3 slave clock idle low 1w uart 0 sm mode unit calculation / notes default valid values symbol description
figure 7-6 typical signal deviation vs. temperature vdd = 5.0 volts, cx = 10pf, cs = 5~200nf pps film l q 10 qt300 r1.01 21/09/03 figure 7-4 typical resolution vs cx & cs; vdd = 3.0 volts cs 0 100 200 300 400 500 011213448 cx load resolution per count (ff) 9nf 19nf 43nf 74nf 124nf 200nf figure 7-5 typical resolution vs cx & cs; vdd = 3.0 volts cs 0 25 50 75 100 125 150 0 11213448 cx load resolution per count (ff) 43nf 74nf 124nf 200nf figure 7-7 typical signal vs. cs & temp vdd = 5.0 volts, cx = 10pf, pps film capacitors 0 1000 2000 3000 4000 5000 6000 -10 0 10 20 30 40 50 60 70 80 temperature, c signal, counts 200nf pps 100nf pps 4.7nf pps -5.00% -4.00% -3.00% -2.00% -1.00% 0.00% 1.00% 2.00% 3.00% 4.00% 5.00% -10-5 0 5 10152025303540455055606570758085 temperature, c % deviation
0.43 10.9 x 0.21 - 5.33 - s1 0.15 0.115 3.81 2.92 s - 0.015 - 0.38 r bsc - 0.1 bsc - 2.54 f 0.012 0.008 0.305 0.203 l2 0.07 0.045 1.78 1.14 l1 0.022 0.014 0.559 0.356 l 0.037 0.027 0.94 0.69 q typical - 0.3 typical - 7.62 m 0.4 0.355 10.16 9.02 m 0.325 0.3 8.26 7.62 a 0.28 0.24 7.11 6.1 a notes max min notes max min inches millimeters symbol package type: 8-pin dual-in-line 8 o 0 o 8 o 0 o 0.035 0.02 0.889 0.508 e 0.01 0.007 0.254 0.178 e 0.08 0.07 2.03 1.78 h 0.013 0.004 0.33 0.102 h 0.02 0.012 0.508 0.305 l bsc 0.05 bsc 1.27 f 0.212 0.203 5.38 5.16 m 0.33 0.3 8.38 7.62 a 0.213 0.205 5.41 5.21 a notes max min notes max min inches millimeters symbol package type: 8-pin wide soic l q 11 qt300 r1.01 21/09/03 pin 1 m f l a a m h h e e pin 1 m m q a a s1 s l1 l f r l2 x a
l q copyright ? 2002 qrg ltd. all rights reserved. patented and patents pending corporate headquarters 1 mitchell point ensign way, hamble so31 4rf great britain tel: +44 (0)23 8056 5600 fax: +44 (0)23 8045 3939 admin@qprox.com www.qprox.com north america 651 holiday drive bldg. 5 / 300 pittsburgh, pa 15220 usa tel: 412-391-7367 fax: 412-291-1015 the specifications set out in this document are subject to change without notice. all products sold and services supplied by qr g are subject to our terms and conditions of sale and supply of services which are available online at www.qprox.com and are supplied with ev ery order acknowledgement. qprox, qtouch, qmatrix, qlevel, and qslide are trademarks of qrg. qrg products are not suitable for medical (including life-saving equipment), safety or mission critical applications or other similar purposes. except as expressly set o ut in qrg's terms and conditions, no licenses to patents or other intellectual property of qrg (express or implied) are granted by qrg in c onnection with the sale of qrg products or provision of qrg services. qrg will not be liable for customer product design and customers ar e entirely responsible for their products and applications which incorporate qrg's products.

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